1. Field of the Invention
The present invention relates to a logic device which is re-programmable during its operation. For instance, the invention relates to a logic device, such as a Field Programmable Gate Array (FPGA), suitable for use in exchanges, whose system down should be avoided. The invention makes it possible to add new functions in such exchanges, and also makes it possible to correct any failures occurring in the exchanges without termination operation.
2. Description of the Related Art
FPGAs are Application Specific Integrated Circuits (ASICs) whose functions can be defined by users. The FPGAs are formed of more than one logic circuit (Configurable Logic Block; CLB) including multiple logic components (AND gates and OR gates, or the like), with a sufficient degree of integration. Those logic components and CLBs are combined, in accordance with programs, to perform a variety of functions.
FIG. 14 shows an FPGA having a construction of a conventional logic device. An FPGA 100 in FIG. 14 performs an operation called “configuration” soon after power is turned on, to obtain circuit configuration and maintenance data (CLB configuration data) from an external device (microprocessor or the like) for configuring and maintaining CLBs (circuit configuration units) 103, which perform specific functions, in the FPGA, and to store the obtained data in the memory 102, such as a RAM.
In this memory 102, required pieces of circuit configuration and maintenance data, each corresponding to functions to be implemented, are stored, and based on such data, the CLBs 103 are configured and maintained in the FPGA 100 to perform the above functions. Here, apart from the above-mentioned circuit configuration and maintenance data, the memory 102 also has areas for storing data (connection net data) for wiring the CLBs 103. The CLBs 103 are also automatically connected, using unwired areas, according to the data written in the wiring data storage areas.
When circuit configuration and maintenance data is written in the memory 102 in a conventional device, the address counter 101 writes the data sequentially, starting from the first address of the memory 102, since there is no concept of addresses. If some memory addresses (unused areas) are empty (unused), data indicating that the corresponding CLBs are non-configured (unused) is written therein.
Further, the following patent document 1 shows another technique in another conventional FPGA. This technique provides the FPGA with memory circuits (RAM modules 10 in FIGS. 1 and 2 of the following patent document 1) which selectively operate as a Random Access Memory or a device to perform a product-term (P term) logic, thus facilitating execution of logic functions having multiple inputs. In this technique, one of the foregoing RAM modules 10 serves as a function of one of the CLBs 103 of the FPGA 100 of FIG. 14.
[Patent Document 1]
Japanese Patent Application Laid Open No. HEI 11-243334
In the foregoing conventional FPGAs, however, it is impossible to write circuit configuration and maintenance data in arbitrary addresses specified in the memory 102 which is provided for deciding (configuring and maintaining) the CLBs 103. Therefore, if an additional function needs to be added or a problem in the device needs to be solved, the device is required to be turned off once, and then turned on again, so that all the circuit configuration and maintenance data is reset before rewriting is performed. In this instance, although it is also possible to repeat the configuration operation once again without turning the power off, the FPGA itself is reset (equal to turning off the power).
Accordingly, in order to add some functions in the FPGA or to correct any problems in the FPGA, system down of the corresponding functions has always been necessary, and it has been impossible to perform such processing while the system is in operation.